Instructor: Nader Sehatbakhsh, Assistant Professor, UCLA
TAs: Akshay Joshi (email: akshayjoshi [at] ucla [dot] edu)
Lectures: M-W 2-3:50 PM (PST) @ Online
Office Hours: by appointment*
Textbook: David A. Patterson and John L. Hennessy, Computer Organization and Design: the Hardware/Software Interface: RISC-V Edition
Links: We will use Campuswire and Gradescope in this course. Please use the links posted in CCLE to enroll.
* to schedule an appointment send an email with your name and availability to nsehat@ee.ucla.edu with subject: [M116]Appointment
The aim of this course is to learn the basics of modern microprocessors and their interactions with other units, such as the memory hierarchy and I/O. At the high-level, Computer architecture is the science and engineering of selecting and interconnecting hardware components to create a computer that meets functional, performance, and cost goals. More specifically, in this course you will learn basic principles and techniques in architecting a computer including designing instruction set architecture (ISA), pipeline, and instruction-level parallelism. You will learn these topics in more detail by designing and implementing a multi-stage pipelined, superscalar processor for a simple RISC ISA using Verilog. Further, you will learn a range of architectural techniques used in modern processor design including superscalar design, out-of-order execution, and cache hierarchies.